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1 ? fn8170.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copyright intersil americas inc. 2005, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners x9260 dual supply/low power/256-tap/spi bus dual digitally-controlled (xdcp?) potentiometers features ? dual?two separate potentiometers ? 256 resistor taps/pot?0.4% resolution ? spi serial interface for write, read, and transfer operations of the potentiometer ? wiper resistance, 100 typical @ v+ = 5v, v- = -5v ? 4 nonvolatile data registers for each potentiometer ? nonvolatile storage of multiple wiper positions ? power-on recall. loads saved wiper position on power-up. ? standby current <5a max ?v cc : 2.7v to 5.5v operation ? 50k , 100k versions of end to end resistance ? 100 yr. data retention ? endurance: 100,000 data changes per bit per register ? 24 ld soic ? low power cmos ? power supply v cc = 2.7v to 5.5v v+ = 2.7v to 5.5v v- = -2.7v to -5.5v ? pb-free plus anneal available (rohs compliant) description the x9260 integrates 2 digitally controlled potentiometer (xdcp) on a monolithic cmos integrated circuit. the digitally controlled potentiometer is implemented using 255 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the spi bus interface. each potentiometer has associated with it a volatile wiper co unter register (wcr) and a four nononvolatile data regi sters that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. power-up recalls the contents of the default data register (dr0) to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. functional diagram r h0 r l0 bus r w0 interface and control v cc v ss spi bus address data status write read transfer 50k or 100k versions inc/dec r h1 r l1 r w1 power-on recall wiper counter registers (wcr) data registers (dr0-dr3) interface control v + v- data sheet august 29, 2006
2 fn8170.3 august 29, 2006 detailed functional diagram ordering information part number part marking v cc limits (v) potentiometer organization (k ) temperature range (c) package pkg. dwg. # x9260ts24i x9260ts i 5 10% 100 -40 to +85 24 ld soic (300 mil) m24.3 x9260ts24iz (note) x9260ts zi -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9260us24 x9260us 50 0 to +70 24 ld soic (300 mil) m24.3 x9260us24z (note) x9260us z 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 x9260ts24i-2.7 x9260ts g 2.7 to 5.5 100 -40 to +85 24 ld soic (300 mil) m24.3 x9260ts24iz-2.7 (note) x9260ts zg -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9260us24-2.7 x9260us f 50 0 to +70 24 ld soic (300 mil) m24.3 x9260us24z-2.7 (note) x9260us zf 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 *add "t1" suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. r 0 r 1 r 2 r 3 wiper counter register (wcr) resistor array pot 1 r h1 r l1 r 0 r 1 r 2 r 3 wiper counter register (wcr) r h0 r l0 data 8 r w0 r w1 pot 0 interface and control circuitry v cc v ss 256-taps 50k and 100k cs sck a0 so si hold wp a1 power-on recall power-on recall v + v- x9260
3 fn8170.3 august 29, 2006 circuit level applications ? vary the gain of a voltage amplifier ? provide programmable dc reference voltages for comparators and detectors ? control the volume in audio circuits ? trim out the offset voltage error in a voltage amplifier circuit ? set the output voltage of a voltage regulator ? trim the resistance in wheatstone bridge circuits ? control the gain, characteristic frequency and q-factor in filter circuits ? set the scale factor and zero point in sensor signal conditioning circuits ? vary the frequency and duty cycle of timer ics ? vary the dc biasing of a pin diode attenuator in rf circuits ? provide a control variable (i, v, or r) in feedback circuits system level applications ? adjust the contrast in lcd displays ? control the power level of led transmitters in communication systems ? set and regulate the dc biasing point in an rf power amplifier in wireless systems ? control the gain in audio and home entertainment systems ? provide the variable dc bias for tuners in rf wireless systems ? set the operating points in temperature control systems ? control the operating point for sensors in industrial systems ? trim offset and gain errors in artificial intelligent systems pin configuration so a0 nc v+ v cc r l0 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 hold sck nc nc nc v- v ss r w1 r h1 r l1 soic x9260 nc 14 13 11 12 nc r h0 r w0 cs a1 si wp x9260
4 fn8170.3 august 29, 2006 pin assignments pin descriptions bus interface pins s erial o utput (so) so is a serial data output pin. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. s erial i nput si is the serial data input pin. all opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. data is latched by the rising edge of the serial clock. s erial c lock (sck) the sck input is used to clock data into and out of the x9260. h old (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. d evice a ddress (a1 - a0) the address inputs are used to set the 4-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communic ation with the x9260. c hip s elect (cs ) when cs is high, the x9260 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the pin (soic) symbol function 1 so serial data output for spi bus 2 a0 device address for spi bus. 3 nc no connect. 4 nc no connect. 5 nc no connect. 6 v+ analog supply voltage (positive) 7v cc system supply voltage 8r l0 low terminal for potentiometer 0. 9r h0 high terminal for potentiometer 0. 10 r w0 wiper terminal for potentiometer 0. 11 cs device address for spi bus. 12 wp hardware write protect 13 si serial data input for spi bus 14 a1 device address for spi bus. 15 r l1 low terminal for potentiometer 1. 16 r h1 high terminal for potentiometer 1. 17 r w1 wiper terminal for potentiometer 1. 18 v ss system ground 19 v- analog supply voltage (negative) 20 nc no connect 21 nc no connect 22 nc no connect 23 sck serial clock for spi bus 24 hold device select. pause the spi serial bus. x9260
5 fn8170.3 august 29, 2006 standby state. cs low enables the x9260, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. potentiometer pins r h , r l the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. since there are 2 potentiometers, there are 2 sets of r h and r l such that r h0 and r l0 are the terminals of pot 0 and so on. r w the wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. since there are 2 potentiometers, there are 2 sets of r w such that r w0 is the terminals of pot 0 and so on. supply pins s ystem s upply v oltage (v cc ) and s upply g round (v ss ) the v cc pin is the system supply voltage. the v ss pin is the system ground. analog supply voltages (v+ and v - ) these supplies are the analog voltage supplies for the potentiometer. the v+ supply is tied to the wiper switches while the v- supply is used to bias the switches and the internal p+ substrate of the integrated circuit. both of these supplies set the voltage limits of the potentiometer. other pins n o c onnect no connect pins should be left floating. this pins are used for intersil manufacturing and testing purposes. h ardware w rite p rotect i nput (wp ) the wp pin when low prevents nonvolatile writes to the data registers. principles of operation serial interface the x9260 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked in on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be connected together, since they have three state outpu ts. this can help to reduce system pin count. array description the x9260 is comprised of a resistor array (see figure 1). the array contains the equivalent of 255 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l inputs). at both ends of each arra y and between each resistor segment is a cmos switch connected to the wiper (r w ) output. within each individual array only one switch may be turned on at a time. these switches are cont rolled by a wiper counter register (wcr). the 8-bits of the wcr (wcr[7:0]) are decoded to select, and enable, one of 256 switches (see table 1). power-up and down requirements. at all times, the voltages on the potentiometer pins must be less than v+ and more than v-. during power- up and power-down, vcc, v+, and v- must reach their final values within 1msecs of each other. the v cc ramp rate spec is always in effect. x9260
6 fn8170.3 august 29, 2006 figure 1. detailed potentiometer block diagram device description wiper counter register (wcr) the x9260 contains two wiper counter registers, one for each dcp potentiometer. the wiper counter register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register in struction (serial load); it may be written indirectly by transfer ring the contents of one of four associated data registers via the xfr data register instruction (paralle l load); it can be modified one step at a time by the increment/decrement instruction (see instructio n section for more details). finally, it is loaded with the contents of its data register zero (dr0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9260 is powered- down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. power-up guidelines are recommended to ensure proper loadings of the dr0 value into the wcr. data registers (dr) each potentiometer has four 8-bit nonvolatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper counter register. all operations changing data in one of the data registers is a nonvol atile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiomete r, the data registers can be used as regular memory locations for system parameters or user preference data. bits [7:0] are used to store one of the 256 wiper positions or data (0~255). status register (sr) this 1-bit status register is used to store the system status. wip: write in progress status bit, read only. ? when wip = 1, indicates that high-voltage write cycle is in progress. ? when wip = 0, indicates that no high-voltage write cycle is in progress. serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel bus input counter register inc/dec logic up/dn clk modified sck up/dn r h r l r w 8 8 c o u n t e r d e c o d e if wcr = 00[h] then r w = r l if wcr = ff[h] then r w = r h wiper (wcr) one of two potentiometers (dr0) (dr1) (dr2) (dr3) x9260
7 fn8170.3 august 29, 2006 table 5. wiper counter register, wcr (8-bit), wcr[7:0]: used to store the current wiper position (volatile, v). table 5. data register, dr (8-bit), bit [7:0]: used to store wiper positions or data (nonvolatile, nv). device description instructions i dentification b yte ( id and a ) the first byte sent to the x9260 from the host, following a cs going high to low, is called the identification byte. the most significant four bits of the slave address are a device ty pe identifier. the id[3:0] bits is the device id for the x9260; this is fixed as 0101[b] (refer to table 3). the ad[3:0] bits in the id byte is the internal slave address. the physical device address is defined by the state of the a3 - a0 input pins. the slave address is externally specified by the user. the x9260 compares the serial data stream with the address input state; a successful compare of both address bits is required for the x9260 to successfully continue the command sequence. only the device which slave address matches the incoming device address sent by the master executes the instruction. the a3 - a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . i nstruction b yte ( i[3:0] ) the next byte sent to the x9260 contains the instruction and register pointer information. the three most significant bits are used provide the instruction opcode (i[3:0]). the rb and ra bits point to one of the four data registers of each as sociated xdcp. the least significant bit points to one of two wiper counter registers or pots.the format is shown below in table 4. table 3. identification byte format table 4. instruction byte format wcr7 wcr6 wcr5 wcr4 wcr3 wcr2 wcr1 wcr0 vvvvvvvv (msb) (lsb) bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 nv nv nv nv nv nv nv nv msb lsb id3 id2 id1 id0 a3 a2 a1 a0 0101 (msb) (lsb) device type identifier slave address i3 i2 i1 i0 rb ra 0 p0 (msb) (lsb) instruction data pot selection opcode selection (wcr selection) register x9260
8 fn8170.3 august 29, 2006 device description instructions four of the ten instructions are three bytes in length. these instructions are: ? read wiper counter register ? read the current wiper position of the selected potentiometer, ? write wiper counter register ? change current wiper position of the selected potentiometer, ? read data register ? read the contents of the selected data register; ? write data register ? write a new value to the selected data register. ? read status - this command returns the contents of the wip bit which indica tes if the internal write cycle is in progress. the basic sequence of the th ree byte instructions is illustrated in figure 3. th ese three-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper positio n. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the two potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. the read status register instruction is the only uniq ue format (see figure 5). four instructions require a two-byte sequence to complete. these instructions transfer data between the host and the x9260; ei ther between the host and one of the data registers or directly between the host and the wiper counter register. these instructions are: ? xfr data register to wiper counter register ? this transfers the contents of one specified data register to the associated wiper counter register. ? xfr wiper counter regist er to data register ? this transfers the contents of the specified wiper counter register to the specified associated data register. ? global xfr data register to wiper counter register ? this transfers the contents of all speci- fied data registers to the associated wiper counter registers. ? global xfr wiper counter register to data register ? this transfers the contents of all wiper counter registers to the specified associated data registers. increment/decrement command the final command is increment/decrement (see figures 6 and 7). the increment/decrement command is different from the other commands. once the command is issued and the x9260 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capab ility to the host. for each scl clock pulse (t high ) while si is high, the selected wiper will move one resistor segment towards the r h terminal. similarly, for each scl clock pulse while si is low, the selected wiper will move one resistor segment towards the r l terminal. a detailed illustration of the se quence and timing for this operation are shown. see in struction format for more details. x9260
9 fn8170.3 august 29, 2006 figure 2. two-byte instruction sequence figure 3. three-byte instruction sequence (write) figure 4. three-byte instruction sequence (read) id3 id2 id1 id0 0 a1 a0 i3 i2 i1 rb ra p0 sck si cs 0101 device id internal instruction opcode address register 0 i0 address pot/wcr address 0 0 0 0101 a1 a0 i3 i2 i1 i0 rb ra p0 scl si d7 d6 d5 d4 d3 d2 d1 d0 cs 00 id3 id2 id1 id0 device id internal instruction opcode address register address pot/wcr address 00 wcr[7:0] or data register bit [7:0] 0 0101 a1 a0 i3 i2 i1 i0 rb ra p0 scl si d7 d6 d5 d4 d3 d2 d1 d0 cs 00 id3 id2 id1 id0 device id internal instruction opcode address register address pot/wcr address 00 wcr[7:0] s0 x x x xx xx x don?t care or data register bit [7:0] 0 x9260
10 fn8170.3 august 29, 2006 figure 5. three-byte instruction sequence (read status register) figure 6. increment/decrement instruction sequence figure 7. increment/decrement timing limits wip status bit 0 101 a1 a0 i3 i2 i1 i0 rb ra p0 scl si cs 00 id3 id2 id1 id0 device id internal instruction opcode address register address pot/wcr address 00 0 0 0 00 00 101 1 0 0101 a1 a0 i3 i2 i1 i0 rb ra p0 scl si cs 00 id3 id2 id1 id0 device id internal instruction opcode address register address pot/wcr address 00 i n c 1 i n c 2 i n c n d e c 1 d e c n 0 sck si r w inc/dec cmd issued t wrid voltage out x9260
11 fn8170.3 august 29, 2006 table 5. instruction set note: 1/0 = data is one or zero instruction instruction set operation i3 i2 i1 i0 rb ra 0 p0 read wiper counter register 1 0 0 1 0 0 0 1/0 read the contents of the wiper counter register pointed to by p0 write wiper counter register 1 0 1 0 0 0 0 1/0 write new value to the wiper counter register pointed to by p0 read data register 1 0 1 1 1/0 1/0 0 1/0 read the contents of the data register pointed to by p0 and rb - ra write data register 1 1 0 0 1/0 1/0 0 1/0 write new value to the data register pointed to by p0 and rb - ra xfr data register to wiper counter register 1 1 0 1 1/0 1/0 0 1/0 transfer the contents of the data register pointed to by p0 and rb - ra to its associated wiper counter register xfr wiper counter register to data register 1 1 1 0 1/0 1/0 0 1/0 transfer the contents of the wiper counter register pointed to by p0 to the data register pointed to by rb - ra global xfr data registers to wiper counter registers 0 0 0 1 1/0 1/0 0 0 transfer the contents of the data registers pointed to by rb - ra of all four pots to their respective wiper counter registers global xfr wiper counter registers to data register 1 0 0 0 1/0 1/0 0 0 transfer the contents of both wiper counter registers to their respective data registers pointed to by rb - ra of all four pots increment/decrement wiper counter register 0 0 1 0 0 0 0 1/0 enable increment/decrement of the control latch pointed to by p0 x9260
12 fn8170.3 august 29, 2006 instruction format read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) global transfer data register (dr) to wiper counter register (wcr) cs falling edge device type identifier device addresses instruction opcode wcr addresses wiper position (sent by x9260 on so) cs rising edge 0 1 0 100a1a01001000p0 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 cs falling edge device type identifier device addresses instruction opcode wcr addresses data byte (sent by host on si) cs rising edge 010100a1a01010000p0 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses data byte (sent by x9271 on so) cs rising edge 010100a1a01011rbra0 p0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses data byte (sent by host on si) cs rising edge high-voltage write cycle 0 10100a1a01100rbra 0 p0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge 010100a1a00001rbra00 x9260
13 fn8170.3 august 29, 2006 global transfer wiper counter register (wcr) to data register (dr) transfer wiper counter register (wcr) to data register (dr) transfer data register (dr) to wiper counter reg- ister (wcr) increment/decrement wiper counter register (wcr) read status register (sr) notes: (1) ?a1 ~ a0?: stands for the device addresses sent by the master. (2) wpx refers to wiper position data in the counter register (2) ?i?: stands for the increment operation, si held high during active sck phase (high). (3) ?d?: stands for the decrement operation, si held low during active sck phase (high). cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge high-voltage write cycle 0 10 100a1a01000rbra00 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses cs rising edge high-voltage write cycle 01 0100a1a01110rbra0p0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses cs rising edge 0 1 0 100a1a01101rbra0p0 cs falling edge device type identifier device addresses instruction opcode wcr addresses increment/decrement (sent by master on sda) cs rising edge 0 1 0 1 0 0 a1 a0 0 0 1 0 x x 0 p0 i/d i/d . . . . i/d i/d cs falling edge device type identifier device addresses instruction opcode wcr addresses data byte (sent by x9260 on so) cs rising edge 0 1 0 100a1a0010100010 0 0 0 0 0 0 wip x9260
14 fn8170.3 august 29, 2006 absolute maximum ratings temperature under bias ........................ -65 to +135c storage temperature ............................. -65 to +150c voltage on sck, scl or any address input with respect to v ss ................................. -1v to +7v voltage on v+ (referenced to v ss )........................ 10v voltage on v- (referenced to v ss )........................-10v (v+) - (v-) .............................................................. 12v any v h /r h ..............................................................v+ any v l /r l .................................................................v- lead temperature (soldering, 10 seconds)...... +300c i w (10 seconds)..................................................6ma comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions temp min. max. commercial 0c +70c industrial -40c +85c device supply voltage (v cc ) (4) limits x9260 5v 10% x9260-2.7 2.7v to 5.5v v+ 2.7v to 5.5v v- -2.5v to -5.5v x9260
15 fn8170.3 august 29, 2006 potentiometer characteristics (over recommended operating condit ions unless otherwise stated.) notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expec ted voltage as determined by wiper positi on when used as a potentiometer. (2) relative linearity is utilized to determi ne the actual change in voltage between tw o successive tap positions when used as a potentiometer. it is a measure of the error in step size. (3) mi = rtot / 255 or (r h - r l ) / 255, single pot (4) during power-up v cc > v h , v l , and v w . (5) n = 0, 1, 2, ?,255; m =0, 1, 2, ?, 254. symbol parameter limits test conditions min. typ. max. unit end to end resistance 20 % power rating 50 mw 25c, each pot i w wiper current 3 ma r w wiper resistance 250 wiper current = 1ma, v+ = 3v; v- = -3v r w wiper resistance 150 wiper current = 1ma, v+ = 3v; v- = -3v vv+ voltage on v+ pin x9260 +4.5 +5.5 v x9260-2.7 +2.7 +5.5 vv- voltage on v- pin x9260 -5.5 -4.5 v x9260-2.7 -5.5 -2.7 v term voltage on any v h /r h or v l /r l pin v- v+ v noise -120 dbv ref: 1khz resolution (4) 0.4 % absolute linearity (1) 1mi (3) v w(n)(actual) - v w(n)(expected) relative linearity (2) 0.6 mi (3) v w(n + 1) - [v w(n) + mi ] temperature coefficient 300 ppm/c ratiometric temperature coefficient 20 ppm/c c h /c l /c w potentiometer capacitances 10/10/25 pf see circuit #3 x9260
16 fn8170.3 august 29, 2006 d.c. operating characteristics (over the recommended operating condit ions unless otherwise specified.) endurance and data retention capacitance power-up timing power-up and down requirements the are no restrictions on the sequencing of the bias supplies v cc , v+, and v- provided that all three supplies reach their final values within 1msec of each other. at all times, the voltages on the potentiometer pins must be less than v+ and more than v-. the recall of the wiper position from nonvol atile memory is not in effect until all supplies reach their final value. the v cc ramp rate spec is always in effect. a.c. test conditions notes: (6) this parameter is not 100% tested (7) t pur and t puw are the delays required from the time the (last) power supply (v cc -) is stable until the specif ic instruction can be issued. these parameters are not 100% tested. symbol parameter limits test conditions min. typ. max. units i cc1 v cc supply current (active) 400 af sck = 2.5 mhz, so = open, v cc = 6v other inputs = v ss i cc2 v cc supply current (nonvolatile write) 15maf sck = 2.5mhz, so = open, v cc = 6v other inputs = v ss i sb v cc current (standby) 5 asck = si = v ss , addr. = v ss , cs = v cc = 6v i li input leakage current 10 av in = v ss to v cc i lo output leakage current 10 av out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 1 v v il input low voltage -1 v cc x 0.3 v v ol output low voltage 0.4 v i ol = 3ma v oh output high voltage v cc - 0.8 v i oh = -1ma, v cc +3v v oh output high voltage v cc - 0.4 v i oh = -0.4ma, v cc +3v parameter min. units minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. units test conditions c out (6) output capacitance (so) 8 pf v out = 0v c in (6) input capacitance (a0, a1, si, cs , wp , hold , and sck) 6 pf v in = 0v symbol parameter min. max. units t r v cc (6) v cc power-up rate 0.2 50 v/ms t pur (7) power-up to initiation of read operation 1 ms i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 x9260
17 fn8170.3 august 29, 2006 equivalent a.c. load circuit ac timing r h 10pf c l c l r w r total c w 25pf 10pf r l spice macromodel 5v 1462 100pf so pin 2714 3v 1382 100pf so pin 1217 symbol parameter min. max. units f sck ssi/spi clock frequency 2 mhz t cyc ssi/spi clock cycle rime 500 ns t wh ssi/spi clock high rime 200 ns t wl ssi/spi clock low time 200 ns t lead lead time 250 ns t lag lag time 250 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 50 ns t ri si, sck, hold and cs input rise time 2 s t fi si, sck, hold and cs input fall time 2 s t dis so output disable time 0 250 ns t v so output valid time 200 ns t ho so output hold time 0 ns t ro so output rise time 100 ns t fo so output fall time 100 ns t hold hold time 400 ns t hsu hold setup time 100 ns t hh hold hold time 100 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs 10 ns t cs cs deselect time 2 s t wpasu wp , a0 setup time 0 ns t wpah wp , a0 hold time 0 ns x9260
18 fn8170.3 august 29, 2006 high-voltage wr ite cycle timing xdcp timing symbol table symbol parameter typ. max. units t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. units t wrpo wiper response time after the third (last) power supply is stable 5 10 s t wrl wiper response time after instruction issued (all load instructions) 5 10 s waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x9260
19 fn8170.3 august 29, 2006 timing diagrams input timing output timing hold timing ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh ... cs sck so si addr msb lsb t dis t ho t v ... ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo x9260
20 fn8170.3 august 29, 2006 xdcp timing (for all load instructions) write protect and device address pins timing ... cs sck si msb lsb vwx t wrl ... so high impedance cs wp a0 a1 t wpasu t wpah (any instruction) x9260
21 fn8170.3 august 29, 2006 applications information basic configurations of electronic potentiometers application circuits v r rw +v r i three- terminal potentiometer; variable voltage divider two-terminal variable resistor; variable current noninverting amplifier voltage regulator offset voltage adjustment comparator with hysterisis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) v ll = {r 1 /(r 1 +r 2 )} v o (min) 100k 10k 10k 10k -12v +12v tl072 + ? v s v o r 2 r 1 } } x9260
22 fn8170.3 august 29, 2006 application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + ? v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k + ? v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o x9260
23 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8170.3 august 29, 2006 x9260 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 0 8 0 8 - rev. 1 4/06

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